ARM Vector Table Location

Vector table could be controlled by ARM co-processor's System Control Register Bit 13


[13] V Vectors bit

This bit selects the base address of the exception vectors:

- 0 Normal exception vectors, base address 0x00000000. Software can remap this base address using the VBAR.

- 1 High exception vectors, base address 0xFFFF0000. This base address is never remapped.


Example

MRC     p15, 0, r1, c1, c0, 0      ; c1 Sys Ctrl Reg.
BIC     r1, r1, #0x2000            ; vector base to 0x00000000 or VBAR
MCR     p15, 0, r1, c1, c0, 0

LDR     r0, =Vectors               ; set VBAR, vector base to "Vector"
MCR     p15, 0, r0, c12, c0, 0



MRC     p15, 0, r1, c1, c0, 0      ; c1 Sys Ctrl Reg.
ORR     r1, r1, #0x2000            ; vector base to 0xFFFF0000
MCR     p15, 0, r1, c1, c0, 0

Reference
Cortex-A7 TRM, section 4.3.27
http://lists.denx.de/pipermail/u-boot/2014-November/195139.html