AHCI

AHCI Implementation
drivers/ata/ahci_platform.c
drivers/ata/libahci.c
implements most ata_port_operations operations

ahci_init_one,
  memory mapping
  hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];  AHCI_PCI_BAR_STANDARD

static inline void __iomem *__ahci_port_base(struct ata_host *host,
     unsigned int port_no)
{
struct ahci_host_priv *hpriv = host->private_data;
void __iomem *mmio = hpriv->mmio;

return mmio + 0x100 + (port_no * 0x80);
}

hpriv->mmio points to the HBA memory registers,  pointed by ABAR(AHCI Base Address).
 __ahci_port_base gets the port register.

Command table is initialized in ahci_port_start(), pp->cmd_tbl = mem;

Below maps to AHCI spec v3.3, port registers.
PORT_LST_ADDR = 0x00, /* command list DMA addr */
PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
PORT_IRQ_STAT = 0x10, /* interrupt status */
PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
PORT_CMD = 0x18, /* port command */
PORT_TFDATA = 0x20, /* taskfile data */
PORT_SIG = 0x24, /* device TF signature */
PORT_CMD_ISSUE = 0x38, /* command issue */
PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
PORT_FBS = 0x40, /* FIS-based Switching */
PORT_DEVSLP = 0x44, /* device sleep */